Dec 07, 2022 23:30:00

What is the next wave of 'Moore's Law' that Intel thinks?

'Moore's Law' states that 'the integration density of semiconductors will double in 18 to 24 months, and even if the performance of chips doubles, further miniaturization will proceed', Gordon, one of the founders of Intel Moore predicted the future in 1965.

Ann B. Kelleher, General Manager of Technology Development at Intel, talks about the 'wave' that follows Moore's Law.

Intel's Take on the Next Wave of Moore's Law - IEEE Spectrum
https://spectrum.ieee.org/whats-next-for-moores-law

According to Mr. Kelleher, 'Moore's Law' refers to 'increasing the degree of integration of functions', which is equivalent to ' optimization of system technology (STCO) ' in the next 10 to 20 years. About. From the workload that the product should support and its software, to the system architecture, the silicon required in the package, and the semiconductor manufacturing process, we will develop outside-in methods that consider solutions based on the needs of society and customers. By doing so, ``we will optimize all the elements so that we can get the best answer in the final product,'' says Kelleher.

STCO has become an option because it divides functions that were previously contained in a single chip into small functional chips, chiplets, each of which is manufactured using the most suitable semiconductor process technology, and is capable of achieving high bandwidth. Being able to connect is a big factor.

As a practical example of STCO, Mr. Kelleher mentioned the Ponte Vecchio processor , which is the heart of the supercomputer 'Aurora'. The Ponte Vecchio processor consists of 47 active chiplets and 8 thermally conductive blanks, connected by advanced 2.5D packaging technology and 3D stacking.

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At

IEDM 2022 , it is announced that Intel engineers have increased the density of 3D hybrid bonding technology by 10 times compared to the 2021 report. Increased connection density means that more chip functions can be decomposed into chiplets, allowing STCO to achieve even greater results. The hybrid bond pitch, which indicates the distance between interconnects , is just 3 microns, allowing more cache to be separated from the processor core. According to Kelleher, if the bond pitch can be shrunk from 2 micrometers to 100 nanometers, logic functions that currently must be on the same silicon can also be separated.

Kelleher pointed out that interconnect technology will be the biggest change in future semiconductor process technology. Intel plans to introduce a technology called 'PowerVia' in 2024. PowerVia will move the chip's power delivery network below the silicon, reducing logic cell size and reducing power consumption.

STCO is still in its early stages, and the electrical circuit design (EDA) tool is working on STCO's predecessor, 'design technology optimization (DTCO),' which is optimized for logic cell level and functional block level. It is said that emphasis is placed. Mr. Kelleher said, ``In the future, attention will be focused on methods and tools to realize STCO.''

Kelleher's new Intel roadmap looks like this. The new transistor architecture RibbonFET and PowerVia will be introduced in the `` Intel 20A '' scheduled to be manufactured from the first half of 2024. Mr. Kelleher, who was asked about the risks of the new technology, answered, ``I think there is a big advantage because we can realize RibbonFET technology by moving to PowerVia.'' It seems that PowerVia's test using FinFET, which is a conventional architecture, was going well and was able to accelerate the development work.

Regarding the future of transistors, the design of planar transistors survived from 1960 to around 2010, and its successor, FinFET, is still alive. I think that it will be laminated at some point.”