Dec 03, 2021 15:00:00

15 new specifications will be added to RISC-V, strengthening functions related to AI, machine learning, and IoT applications

RISC-V International, a standardization body for the instruction set architecture ' RISC-V ' provided by an open source license, has newly added 40 extended specifications for RISC-V vector specifications, hypervisor specifications, and scalar encryption functions. Announced that it has approved 15 new specifications, including. The new specifications approved this time are said to bring new possibilities to application developers for artificial intelligence (AI), machine learning, the Internet of Things (IoT), self-driving cars, and data centers.

RISC-V International Ratifies 15 New Specifications, Opening Up New Possibilities for RISC-V Designs --RISC-V International
https://riscv.org/announcements/2021/12/riscv-ratifies-15-new-specifications/

The RISC-V vector specification is a function used to speed up the calculation of data-intensive processes such as machine learning inference related to music, audio, and video. Vector specifications are used in a variety of edge computing applications, from consumer IoT devices to industrial machine learning applications, but the new RISC-V International is an approach that efficiently processes the latest machine learning algorithms. Is newly approved. 'The new vector specifications added to RISC-V will change the way we think about vector design,' said Dave Ditzel, founder and CEO of Esperanto Technologies, which develops RISC-V-based AI chips. I am commenting.

by Chiara Coetzee

The hypervisor specification is a function that virtualizes the supervisor-level architecture and streamlines the hosting of guest OSes on the hypervisor. The hypervisor specification is required to implement virtual machines in RISC-V. The newly approved hypervisor specification has been described as facilitating the adoption of RISC-V in data center and desktop environments and can be a key factor in enabling virtualization capabilities.

The scalar encryption feature accelerates cryptographic workloads in memory savings, and a newly approved extension allows the implementation of standard cryptographic hash and block cipher algorithms, with standard instructions in some situations. It is said that encryption that can realize an order of magnitude speed has become possible. This will achieve secure and efficient high-speed encryption in IoT and embedded devices, significantly lowering the entry barrier, said Ben Marshall, a member of the RISC-V Technical Steering Committee, 'Everyone is important. Cryptographic algorithms can be efficiently implemented on all classes of CPUs. '' In addition to performance benefits, these new extensions can be implemented at a very low cost, so companies minimize common cryptographic algorithms. It can also be integrated into connected devices. '